Schloss Schönbrunn

Schönbrunn Palace, Former Imperial Summer Residence - Photo by Christer van der Meeren

Heldenplatz, Volksgarten and Parlament

View of the Ringstrasse from the roof of the Burgtheater - Photo by WienTourismus/Christian Stemper

ASYNC 2018 - May 13-16 2018
Vienna, Austria

24th IEEE International Symposium on Asynchronous Circuits and Systems

The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design. The 24th symposium will be hosted by TU Wien in Vienna, Austria.

Collocated with FAC’18



Classical Control for Quantum Processors: a Cryo-CMOS Perspective
by Edoardo Charbon, EPFL

Abstract - Quantum computing holds the promise to solve intractable problems using processors that exploit quantum physics concepts, such as superposition and entanglement. A quantum processor’s core is an array of quantum bits (qubits) that can be implemented in a number of solid-state technologies, including silicon. The quantum processor needs to be controlled and read out by a classical processor operating on the qubits in real time, several millions of times per second. Due to the extremely weak signals involved in the process, ultra-low-noise, highly sensitive circuits and systems are needed, along with very precise timing capability. We advocate the use of CMOS technologies to achieve these goals, whereas the circuits will be operated at deep-cryogenic temperatures, we call these circuits, collectively, cryo-CMOS classical control. In the keynote, the challenges of designing and operating complex circuits and systems at 4K and below will be outlined, along with preliminary results achieved in the control and read-out of qubits by ad hoc integrated circuits that were optimized to operate at low power in these conditions. The talk will conclude with a perspective on the field and its trends.

Edoardo Charbon (SM’00 F’17) received the Diploma from ETH Zurich, the M.S. from the University of California at San Diego, and the Ph.D. from the University of California at Berkeley in 1988, 1991, and 1995, respectively, all in electrical engineering and EECS. He has consulted with numerous organizations, including Bosch, X-Fabs, Texas Instruments, Maxim, Sony, Agilent, and the Carlyle Group. He was with Cadence Design Systems from 1995 to 2000, where he was the Architect of the company's initiative on information hiding for intellectual property protection. In 2000, he joined Canesta Inc., as the Chief Architect, where he led the development of wireless 3-D CMOS image sensors. Since 2002 he has been a member of the faculty of EPFL, where is a full professor since 2015. From 2008 to 2016 he was with Delft University of Technology’s as Chair of VLSI design. He has been the driving force behind the creation of deep-submicron CMOS SPAD technology, which is mass-produced since 2015 and is present in telemeters, proximity sensors, and medical diagnostics tools. He has also been the strong proponent of using cryogenic CMOS (cryo-CMOS) circuits and systems for the classical control of quantum processors, so as to achieve scalable quantum computers. His interests span from 3-D vision, FLIM, FCS, NIROT to super-resolution microscopy, time-resolved Raman spectroscopy, and cryo-CMOS circuits and systems for quantum computing. He has authored or co-authored over 250 papers and two books, and he holds 20 patents. Dr. Charbon is a distinguished visiting scholar of the W. M. Keck Institute for Space at Caltech, a distinguished lecturer of the IEEE Photonics Society, a fellow of the Kavli Institute of Nanoscience Delft, and a fellow of the IEEE.

Design of Asynchronous Genetic Circuits
by Chris J. Myers, University of Utah

Abstract - Researchers are now able to engineer synthetic genetic circuits for a range of applications in the environmental, medical, and energy domains. Crucial to the success of these efforts is the development of methods and tools for genetic design automation (GDA). While inspiration can be drawn from experiences with electronic design automation (EDA), design with a genetic material poses several challenges. In particular, genetic circuits are composed of very noisy components making their behavior more asynchronous, analog, and stochastic in nature. This talk presents our research in the development of the GDA tool, iBioSim, which leverages our past experiences in asynchronous circuit synthesis and formal verification to address these challenges. The iBioSim tool enables the synthetic biologist to construct models in a familiar graphical form, analyze them using a variety of methods that leverage efficient abstractions, visualize their analysis results using an intuitive interface, and ultimately synthesize a genetic implementation from a library of genetic parts. Each step of this design process utilizes standard data representation formats enabling the ready exchange of results.

Chris J. Myers received the B.S. degree in Electrical Engineering and Chinese history in 1991 from the California Institute of Technology, Pasadena, CA, and the M.S.E.E. and Ph.D. degrees from Stanford University, Stanford, CA, in 1993 and 1995, respectively. He is a Professor in the Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT. Dr. Myers is the author of over 150 technical papers and the textbooks Asynchronous Circuit Design and Engineering Genetic Circuits. He is also a co-inventor on 4 patents. His research interests include asynchronous circuit design, formal verification of analog/mixed signal circuits and cyber-physical systems, and modeling, analysis, and design of genetic circuits. Dr. Myers received an NSF Fellowship in 1991, an NSF CAREER award in 1996, and best paper awards at the 1999 and 2007 Symposiums on Asynchronous Circuits and Systems. Dr. Myers is a Fellow of the IEEE, and he is a Member of the Editorial Board for ACS Synthetic Biology, Engineering Biology, Synthetic Biology, and IEEE Life Sciences Letters and has served on the Editorial Boards for the IEEE Transactions on VLSI Systems, IEEE Design & Test Magazine, and Springer journal on Formal Methods in System Design. Dr. Myers has also served as an editor for the Systems Biology Markup Language (SBML) standard and is on the steering committee for the Synthetic Biology Open Language (SBOL) standard.

A Roadmap for Saving Async from Irrelevance
by Mike Davies, Intel Labs

Abstract - As this community well knows, asynchronous design methodologies are not new. Some of the earliest computers were designed without clocks, and commercial applications of asynchronous designs have unremarkably dotted the history of VLSI systems over the past 50 years. The predominant view among technologists today is that asynchronous techniques have rarely, if ever, provided unambiguous value for their applications in a way that would outperform synchronous approaches. Regardless of the truth of that view, the asynchronous community needs to fundamentally shift its perspectives and practices if asynchronous design methods are ever to become relevant for mainstream use. In this talk I offer a straw man proposal for how we can rescue asynchronous from the doldrums of VLSI design.

Mike Davies has led the design and development of many of the industry’s most advanced asynchronous chips over the past 18 years. As Fulcrum Microsystems’ Director of Silicon Engineering, he and his team pioneered high performance, commercially viable asynchronous design methodologies. Over that time, Fulcrum produced five generations of switch products with leading bandwidth, latency, power, and features. Today, as Director of Intel’s Neuromorphic Research Lab, he continues to advance asynchronous design practice, most visibly with its recent application to the Loihi neuromorphic research chip.


Organizing Committee

General Chairs

Andreas Steininger, TU Vienna, Austria

Matthias Fuegger, CNRS & ENS Paris-Saclay, France

Program Chairs

Milos Krstic, IHP and University of Postdam, Germany

Ian W. Jones, Oracle Labs, USA

Industrial Liaison Chair

Eckhard Grass, IHP and Humboldt-Universität Berlin, Germany

Prasad Prakash Joshi, Intel Labs, USA

Publications Chair

Erik Brunvand, University of Utah, USA

Publicity Chair

Luciano Lavagno, Politecnico Torino, Italy

Publicity Chair (Asia)

Hong Chen, Tsinghua University, China

Finance Chair

Traude Sommer, TU Vienna, Austria

Local Arrangements Chairs

Florian Huemer, TU Vienna, Austria

Jürgen Maier, TU Vienna, Austria

Program Committee

John Bainbridge, NetSpeed Systems, USA

Peter Beerel, University of Southern California, USA

Edith Beigne, CEA-Leti, France

Davide Bertozzi, University of Ferrara, Italy

Kwabena Boahen, Stanford University, USA

Erik Brunvand, The University of Utah, USA

Ney Calazans, Pontificia Universidade Católica do Rio Grande do Sul, Brazil

Jean-Frederic Christmann, CEA-Leti, France

Jordi Cortadella, Universitat Politècnica de Catalunya, Spain

Shomit Das, AMD Research, USA

Georgios Dimou, Intel, USA

Reuven Dobkin, vSync Circuits, Israel

Xin Fan, RWTH Aachen, Germany

Laurent Fesquet, TIMA, France

Jim Garside, The University of Manchester, UK

Gennette Gill, D. E. Shaw Research, USA

Ran Ginosar, Technion, Israel

Mark Greenstreet, University of British Columbia, Canada

Masashi Imai, Hirosaki University , Japan

William Koven, REM, USA

Luciano Lavagno, Politecnico di Torino , Italy

Christoph Lenzen, MPI Saarbrücken, Germany

Rajit Manohar, Cornell University, USA

Joycee Mekie, IIT Gandhinagar, India

Andrey Mokhov, Newcastle University, UK

Matheus Moreira, Chronos Tech, USA

Chris Myers, University of Utah, USA

Duarte Oliveira, Instituto Tecnológico de Aeronáutica, Brazil

Julian Pontes, ARM Research, UK (Brazil)

Marly Roncken, Portland State University, USA

Arash Saifhashemi, Intel, USA

Hiroshi Saito, The University of Aizu, Japan

Montek Singh, University of North Carolina at Chapel Hill, USA

Christos Sotiriou, University of Crete, Greece

Jens Sparso, Technical University of Denmark, Denmark

Ken Stevens, The University of Utah, USA

Pascal Vivet, CEA-Leti, France

Zhao Wang, University of Texas at Dallas, USA

Eslam Yahya, Zewail City of Science and Technology, France

Alex Yakovlev, Newcastle University, UK

Suwen Yang, Oracle, USA

Tomohiro Yoneda, National Institute of Informatics, Japan

Call for Papers

Authors are invited to submit papers on any aspect of asynchronous design, ranging from design, synthesis, and test to asynchronous applications. Topics of interest include:

Paper Format and Submission

Submissions for regular and special topics must report original scientific work, in 6-8 pages IEEE double-column conference format (single-spaced, 10pt or larger font size), with author information concealed. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings.

"Fresh Ideas" / Student Poster

We solicit 1-2 page submissions that present "fresh ideas" in asynchronous design, not yet ready for publication. These will go through a separate light-weight review process. Accepted submissions will be assembled in a binder and handed out at the workshop. We also invite students to present a poster on their research, co-authored with their advisor, and to submit a one page abstract that will receive a light-weight review.

Industrial Papers / Tools & Demos

ASYNC 2018 will include papers and tutorials from industry on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. The topics are specifically targeted at industry and include:

We solicit 1-2 page submissions for the workshop, IEEE double-column conference format. These papers will go through a separate light-weight review process. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings. We also solicit tools and demos for presentation at the conference.

Download PDF Version

Author Information

Submission Website

To make a submission for ASYNC 2018, go to our submission page You will need to login or register and login. Once logged in, from the login screen, click on the Make a new Submission link.

Paper Template

Please use the templates provided by the IEEE (link) for all papers submitted to ASYNC 2018.

Important Dates

Regular Papers

Industrial Papers, Fresh Ideas Papers, Posters, Tools & Demos

Abstract Registration

November 26, 2017
December 3, 2017
December 10, 2017  

February 14, 2018

Paper Submission

December 3, 2017
December 10, 2017

(Abstracts only)

Notification of Acceptance

February 7, 2018 

February 28, 2018

Publication Ready Version

March 10, 2018 

March 10, 2018

Submit a Paper

Conference Venue

ASYNC 2018 will be held in the Radisson Blu Park Royal Palace Hotel located right next to the Technical Museum and the famous Schönbrunn Palace. More information about the hotel is available in their website. The city center and other attractions can easily be reached by tram (directly in front of the hotel) or underground (a few minutes away). For more information about the city and its attractions please visit this website.

Radisson Blu Park Royal Palace Hotel, Vienna
Schlossallee 8, A-1140 Wien (Austria)
[Google Maps]
Phone: +43 (1) 89 11 0
Email: park.royal.palace@austria-trend.at

Arrival and Directions

The venue can be conveniently reached with U-Bahn (subway) or tram. Coming from the VIE airport, the simplest public transport route is to take the suburban railway S7 (cheaper) or the dedicated City Airport Train CAT (faster) to the subway station "Landstraße (Bhf. Wien Mitte)" (for more details and current fares check this website). From Landstraße, you can take the U-Bahn U4 (direction "Hütteldorf") to "Schönbrunn", from which it is a 15 min walk to the hotel. Alternatively, you can take U4 to "Hietzing" (the stop after Schönbrunn) and take the tram line 60 (direction "Westbahnhof") or 10 (direction "Dornbach") to the stop "Penzinger Straße", which is right next to the hotel. When arriving by train or bus at Wien Hauptbahnhof, you can take tram line 18 to Wien Westbahnhof and from there tram line 60 or 52 to "Penzinger Straße".

Alternative Hotels

Social Event / Conference Dinner

The conference dinner will be hosted in the courtyard of the "Haus der Musik" (House of Music) museum. Established in the year 2000, it is the first museum of sound and music in Austria. If you would like to visit the exhibition during your stay in Vienna contact us for free tickets.

Our Sponsors

(as of December 7th)


Institute of Computer Engineering - TU Wien
Embedded Computing Systems Group [link]
Treitlstasse 3, 2nd floor, A-1040 Wien (Austria) [Google Maps]
Phone: +43(1)58801-18203
Email: info@async2018.wien